View AD2S44-TM11B_8231520.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

low cost, 14 - bit , dual channel synchro/resolver -to- digital converter data sheet ad2s44 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by imp lication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 1989 C 2011 analog devices, inc. all rights reserved. f eatures low per - channel cost 32- lead dil hybrid package 2.6 arc minute accuracy 14- bit resolution built - in test independent reference inputs high tracking rate a pplications gimbal/gyro control systems robotics engine controllers coordinate conversion mili tary servo control systems fire control systems avionic systems antenna monitoring cnc machine tooling g eneral d escription the ad2s44 is a 14- bit dual channel, continuous tracking synchro/ resolver - to - digital c onverter . it has been designed specifically for applications where space, weight, and cost are at a premium. each 32 - lead hybrid device contains two independent type ii servo loop tracking converters. the ratio metric conversion technique employed provides excellent noise immunity and toleranc e of long lead lengths . the core of each c onversion is performed by state - of - the - art mono - lithic, integrated circuits manufactured by the analog devices, inc., proprietary bimos ii process , which combines the advantages of low power cmos digital logic with bipolar linear circuits. the use of these ics keep s the internal component count low and ensures high reliability. the built - in tes t ( bit ) facility can be used in fail safe systems to provide an i ndication of whether the converter is track ing accurately. each channel incorporates a high accuracy differential con di - tioning circuit for signal inputs providing more tha n 74 db of common - mode rejection. options are available for both synchro and resolve r format inputs. the converter output is via a three - state transparent latch allowing data to be read without interruption of the converter operation. the a/ b and oe control lines select the channel and present the digital position to the common data outputs . the ad2s44 also features independent reference inputs where dif ferent reference frequencies can be used for each channel. all components are 100% tested at ? 55c, +25c, and +125c. devices are processed to high reliability screening standards and receive further levels of testing and screening to ensure high levels of reliability . f unctional block d iagram ad2s44 reference conditioner synchro/ reso l ver conditioner phase- sensitive detec t or three- sta te output la tches db1 (msb) t o db14 (lsb) phase- sensitive detec t or high speed sin/cos mul tiplier bui l t -in test detection error amp up-down counter up-down counter integr a t or vco vco integr a t or error am p high speed sin/cos mul tiplier synchro/ reso l ver conditioner reference conditioner s3 (a) r hi (a) r lo (a) r hi (b) r lo (b) +v s ?v s gnd s4 (a) s1 (a) s2 (a) s3 (b) s4 (b) s1 (b) s2 (b) oe a/b bit 02947-001 figure 1 .
ad2s44 data sheet rev. b | page 2 of 12 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? table of contents .............................................................................. 2 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ............................. 6 ? theory of operation ........................................................................ 7 ? connecting the converter ........................................................... 7 ? channel select (a/ b ) ................................................................... 7 ? output enable ( oe ) ......................................................................8 ? built-in test ( bit ) .........................................................................8 ? scaling for nonstandard signals .................................................9 ? dynamic performance ..................................................................9 ? acceleration error .........................................................................9 ? reliability ..................................................................................... 10 ? processing for high reliability (b suffix) ............................... 10 ? other products ........................................................................... 10 ? outline dimensions ....................................................................... 11 ? ordering guide .......................................................................... 11 ? ordering information ................................................................ 11 ? revision history 10/11rev. a to rev. b changes to figure 1 .......................................................................... 1 changes to figure 3 .......................................................................... 7 08/08rev. 0 to rev. a updated format ................................................................ universal changes to specifications section .................................................. 3 changes to absolute maximum ratings section ......................... 5 deleted standard processing section ............................................. 7 changes to processing for high reliability section and other products section ................................................................. 10 updated outline dimensions ....................................................... 11 changes to ordering guide .......................................................... 11 changes to ordering information ............................................... 11 10/89revision 0: initial version
data sheet ad2s44 rev. b | page 3 of 12 specifications v s = 1 5 v at t a = 25c, unless otherwise noted. table 1. parameter min typ max unit tes t conditions/comments performance accuracy 1 ad2s44 - umb 2 ? 4.0 + 4.0 arc m in utes ? 55c to +125c ? 2.6 + 2.6 arc minutes ? 25c to +85c ad2s44 - tmb 2 ? 4.0 + 4.0 arc minutes ? 55c to +125c tracking rate 20 rev/sec resolution (1 lsb = 1.3 arc min utes ) 14 bits output coding parallel natural binary repeatability 1 lsb signal/reference frequency 400 2600 hz bandwidth 100 hz signal inputs signal voltage 11.8 or 90 v rms see the ordering information section input impedance 90 v signal 200 k? resistive t olerance 2% 11.8 v signal 26 k ? common - mode rejection 74 db common - mode range 90 v signal 250 v dc 11.8 v signal 60 v dc reference inputs reference voltage 26 or 115 v rms see the or dering information section input impedance 115 v 270 k? resistive t olerance 5% 26 v 270 k? common - mode range 115 v 210 v dc 26 v 210 v dc acceleration constant 62,000 sec C2 step response large step 1 , 2 63 75 ms 179 to 1 lsb of error small step 1 , 2 25 30 ms 2 to 1 lsb of error power lines +v s = +15 v 1 , 2 75 80 ma quiescent condition C v s = ? 15 v 1 , 2 40 45 ma quiescent condition power dissipation 1.7 1.9 w quiescent condition digital inputs oe v il 0.7 v dc i il = 5 a v ih 2.0 v dc i ih = 5 a a/ b v il 0.7 v dc i il = 1.2 ma v ih 2.0 v dc i ih = C60 a digital outputs (db1 to db14) v ol 1 , 2 0.4 v dc i il = 1.2 ma v oh 1 , 2 2.4 v dc i oh = 60 a three -s tate leakage current 40 a drive capability 3 lsttl l oads
ad2s44 data sheet rev. b | page 4 of 12 parameter min typ max unit tes t conditions/comments data transfer see figure 6 time to data stable (after negative edge of oe or change of level of a/ b ) 640 ns t s time to data in high impedance state (after positive edge of oe ) 200 ns t r ti me for repetitive strobing of selected channel 200 ns t p built - in test output ( bit ) sense active l ow low = e rror condition v ol 0.4 v dc i ol = 3.2 ma v oh 2.4 v dc i oh = ? 160 a drive capability 8 lsttl l oads error condition set 55 lsb error condition cleared 45 lsb 1 specified over temperature range, ? 55c to +125c , and for: (a) 10% signal and reference amplitude variation; (b) 10% signal and reference harmonic distortion; (c) 5% power supply variation; and (d) 10% variation in reference frequency. 2 these parameters are 100% tested at nominal val ues of power supplies, input signal voltages , and operating frequency. all other parameters are guaranteed by design, not tested.
data sheet ad2s44 rev. b | page 5 of 12 absolute maximum rat ings table 2. parameter rating +v s to gnd +17.25 v dc C v s to gnd ? 17.25 v dc any logic input to gnd +6.0 v dc (max imum ) any logic input to gnd ? 0.4 v dc (min imum ) maximum junction temperature 150c s1, s2, s3, s 4 pins (line -to - line) 1 90 v option 600 v dc 11.8 v option 80 v dc s1, s2, s3, s4 pins to gnd 90 v option 600 v dc 11.8 v opti on 80 v dc r hi pins to r lo pins 26 v, 115 v options 600 v dc r hi pins to r lo pins to gnd 26 v, 115 v options 600 v dc storage temperature range ? 65c to +150c operating temperature range ? 55c to +125c 1 on synchro input options, line - to - line voltage refers to the differential voltages of s2 (a)/s2 (b) to s1 (a)/s1 (b) , s1 (a)/s1 (b) to s3 (a)/s3 (b) , an d s3 (a)/s3 (b) to s2 (a)/s2 (b) . on resolver input options, line - to - line levels refer to the s1 (a)/ s1 (b) to s3 (a)/s3 (b) and s2 (a)/s2 (b) to s4 (a)/s4 (b) voltages. stresses above those listed under absol ute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad2s44 data sheet rev. b | page 6 of 12 pin configuration and function descrip tions 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 32 31 30 29 28 27 26 25 24 23 22 21 20 19 15 16 18 17 db9 db10 db 1 1 db14 (lsb) db13 db12 db8 db6 db5 db4 db1 (msb) db2 db3 oe a/b bit s3 (a) r hi (a) r lo (a) +v s ?v s gnd s3 (b) s4 (a) s4 (b) s1 (a) s1 (b) s2 (a) s2 (b) r hi (b) r lo (b) db7 ad2s44 t op view (not to scale) 02947-003 figure 2 . pin configuration table 3 . pin function descriptions pin no. mnemonic description 1 to 7 db8 to db14 (lsb) parallel output data bits. 8 oe output enable input. 9 a/ b channel a or channel b select input. 10 bit built - in tes t error output. 11 r lo (a) input pin for channel a reference low. 12 r hi (a) input pin for channel a reference high. 13 to 16 s4 (a) to s1 (a) channel a input signal. 17 to 20 s1 (b) to s4 (b) channel b input signal. 21 r hi (b) input pin for channel b reference high. 22 r lo (b) input pin for channel b reference low. 23 gnd power supply ground. this pin is electrically connected to the case. 24 C v s negative power supply. 25 +v s positive power supply. 26 to 32 db1 (msb) to db7 parallel output data b its.
data sheet ad2s44 rev. b | page 7 of 12 theory of operation the ad2s44 operate s on a tracking principle. the output digital word continually trac ks the position of the synchro/ resolver shaft without the need for external convert commands and status wait loops. as the transducer moves through a position equivalent to the least significant bit weighting, the output digital word is updated. each channel is identical in operation, sharing power supply and output pins. both channels operate conti nuously and indepen dently of each other. the digital output from either channel is available after switching the channel select and output enable inputs . if the device is a synchro - to - digital converter, the 3 - wire synchro output is connected to the s1, s2 , and s3 pins on the unit, and a solid - state scott t input conditioner convert s thes e signals into resolver format given by v 1 = k e 0 sin t sin v 2 = k e 0 sin t cos where: is the angle of the synchro shaft. e 0 sin t is the refer ence signal. k is th e transformation ratio of the input signal conditioner. if the unit is a resolver - to - digital converter, th e 4 - wire resolver output is connected directly to the s 1 , s2 , s3, and s4 pins on the unit. to understand the conversion process, assume that the curr ent word state of the up - down co unter is ? . v 1 is multiplied by cos ? , and v 2 is multiplied by sin ? to give the following : k e 0 sin t sin cos ? k e 0 sin t cos sin ? these signals are subtracted by the error amplifier to give k e 0 sin t (sin cos ? ? cos sin ? ) or k e 0 sin t sin ( ? ? ) a phase sensitive detector, integrator, and voltage - controlled oscillator (vco) form a closed - loop s ystem that seeks to null sin ( ? ?). when this is accomplished, the word state of the up - down co unter (?) equals the synchro/resolver shaft angle ( ) , to within the rated accuracy of the converter. connecting the conve rter the power supply voltages connected to ? v s and + v s are to be 15 v and can not be reversed. it is suggested that a p arallel combination of a ceramic 100 nf capacito r and a tantalum 6 .8 f capacitor be placed from each of the supply pins to gnd. the pin marked gnd is connected electrically to the case and is to be taken to 0 v potential in the system. the digital output is taken from pin 26 to pin 32 and from pin 1 to pin 7. pin 26 is the msb , and pin 7 is the lsb. the reference connections are made to the r hi pins and the r lo pins . in the case of a synchro, the signals are connected to the s1, s2, and s3 pins , according to the following convention: e s1 ? s3 = e rlo ? rhi sin t sin e s3 ? s2 = e rlo ? rhi sin t sin ( ? 120) e s2 ? s1 = e rlo ? rhi sin t sin ( C 240) for a resolver, the signals are connected to the s1, s2 , s3, and s4 pins , according to the following convention: e s1 ? s3 = e rlo ? rhi sin t sin e s2 ? s4 = e rlo ? rhi sin t cos channel select (a/ b ) a/ b is the chan nel select input. a l ogic 1 selects c hannel a, and a l ogic 0 selects c hannel b. data becomes valid 640 ns after a/ b is toggl ed. timing information is shown in figure 4 and figure 5 . ad2s44 reference conditioner synchro/ reso l ver conditioner phase- sensitive detec t or three- sta te output la tches db1 (msb) t o db14 (lsb) phase- sensitive detec t or high speed sin/cos mu l tiplier v 1 v 2 bui l t -in test detection error amp up-down counter up-down counter integr a t or vco vco integr a t or error am p high speed sin/cos mu l tiplier synchro/ reso l ver conditioner reference conditioner s3 (a) r hi (a) r lo (a) r hi (b) r lo (b) +v s ?v s gnd s4 (a) s1 (a) s2 (a) s3 (b) s4 (b) s1 (b) s2 (b) oe a/b bit 02947-010 figure 3 . functional b lock d iagram
ad2s44 data sheet rev. b | page 8 of 12 output e nable ( oe ) oe is the outp ut enable input; the signal is active low. when set to logic 1 , db1 to db14 are in high impedance state. when oe is set to logic 0 , db1 to db14 represent the angle of the transducer shaft to within the stated accuracy of the converte r (see bit weights in table 4 ). data becomes valid 640 ns after the oe is switched. timing information is shown i n figure 4 and figure 5 and detailed in tabl e 1 . table 4 . bit weight bit no. weight (degrees) 1 (msb) 180.0000 2 90.0000 3 45.0000 4 22.5000 5 11.2500 6 5.6250 7 2.8125 8 1.4063 9 0.7031 10 0.3516 11 0.1758 12 0.0879 13 0.0439 14 ( lsb ) 0.0220 channe l b v alid * channe l a v alid * t r t s t s oe a/b data bits (1 to 14) * converter d at a output is inhibited from upd a tes during channe l v alid. 02947-005 figure 4 . repetitive reading of one channel oe a/b data bits (1 to 14) dat a v alid * dat a v alid * t r t s t p *converter d at a output is inhibited from upd a tes during channe l v alid. 02947-004 figure 5 . alternative reading of each channe l built - in t est ( bit ) the bit is the built - in test erro r output, which provides an over - velocity or fault indication signal for the channel selected via a/ b . the error voltage of each channel is continuously monitored . w hen the error exceeds 50 bits for the currently se lected chan nel, t he bit output goes low , indicating that an error greater than approx - imately one angular degree exists, and t he data is , therefore , invalid. the bit signal has a built - in hysteresis ; that is, the error required to set the bit is greater than the error required for it to be cleared. the bit is set when the error exceeds 55 lsbs and is cleared when the error goes below 45 lsbs. this mode of operation guarantees that th e bit does not flicker when the error threshold is crossed. the bit is valid for the selected channel approximately 50 ns after the change in the state of a/ b . in most instances, the err or condi - tion that sets the bit must persist for at least one period o f the reference signal prior to the bit responding to the condition. table 5. bit output faul ts condition description power - up transient response the bit return s to a logic high state after the ad2s44 position output synchronizes with the angle input to within 1 . normally, the bit is low at power - up for a period less than or equal to the large signal step response settling time of the ad2s44 after the v s supplies have stabilized to within 5% of their final va lues. step input > 1 the bit return s to a logic high state after the selected channel of the ad2s44 has settled to w ithin 1 of the input angle resulting from an instantaneous step. e xcessive velocity the bit is driven to a logic low if the maximum tracking rate of the ad2s44 is exceeded (20 rps typical). signal failure the bit may be driven to a logic low state if all signal voltages to the selected channel are lost. converter/system failure any failure that causes the ad2s44 to fail to track the input synchro/resolver angles drive s the bit to a logic low. this may include, but is not limited to, acceleration conditions, poor supply voltage regulation, or excessive noise on the signal connections.
data sheet ad2s44 rev. b | page 9 of 12 s caling for nonstandard s ignals a feature of these converters is that the sign al and reference inputs can be resistively scaled to accommodate nonstandard input signal and reference voltages that are outside the nominal 10% limits of the converter. using this technique, it is possible to use a standard converter with a personality card in systems where a wide range of input and reference voltages are encountered. the accuracy of the converter is affected by the matching accu - racies of resistors used for external scaling. for resolver format options, it is critical that the value of the resistors on the s1 (a)/ s1 (b) to s3 (a)/s3 (b) signal input pair be precisely matched to the s4 (a)/s4 (b) to s2 (a)/s2 (b) input pair. for synchro options, the three resistors on the s1, s2, and s3 pins must be matched. in general, a 0.1% mismatch b etween resistor values contribute s an additional 1.7 a rc m inutes of error to the conversion. in addition, imbalances in resistor values can greatly reduce the common - mode reject ion ratio of the signal inputs. to calculate the values of the external scaling resistors, add 2.222 k? for each volt of signal in series with the s 1, s2, s3, and s4 pins (no resistor is required on the s4 pins for synchro options) and add 3 k? extra per volt of reference in series with the r lo pins and the r hi pins. dynamic performa nce in out k a s 2 1 + st 1 1 + st 2 02947-006 figure 6 . transfer function of ad2s44 the transfer function of the converter is as follows: open - loop transfer function 2 1 a in out st st s k + + = 1 1 2 cl osed - loop transfer function a 2 a 1 1 in out k t s k s st st 3 2 1 1 + + + + = w here: k a = 62000 sec C 2 . t 1 = 0.0061 sec . t 2 = 0.001 sec . the gain and phase diagrams are shown in figure 7 and figure 8 . frequenc y (hz) gain (db) 6 3 0 ?15 ?12 ?9 ?6 ?3 10 100 02947-007 figure 7 . gain plot frequenc y (hz) phase (degrees) 180 135 90 45 ?180 ?135 ?90 ?45 0 10 100 02947-008 figure 8 . phase plot accelerat ion error a tracking converter employing a type ii servo loop d oes not suffer any velocity lag. h owever, t here is an additional error due to acceleration. this error is defined using the acceleration constant ( k a ) of the converter k a = input acceleration/e rror in output angle the numerator and denominator must have consistent angular units. for example, if k a is expressed in sec C 2 , the input accelera - tion is to be specified in degrees/sec 2 and the output angle error is to be specified in degrees. alternativ ely, the angular unit of measure can also be in units such as radians, arc minutes, or lsbs.
ad2s44 data sheet rev. b | page 10 of 12 k a does not define maximum acceleration; it defines only the error due to accelerati on. the maximum acceleration of which the ad2s44 keeps track is approximate to 5 k a = 310,000 / sec 2 or about 800 revolutions/sec 2 . k a can be used to predict the output position error due to input acceleration. for example, an acceleration of 50 revolutions/sec 2 with k a = 62 , 000 is calc ulated using the following equation: [ ] = ? ? ? ? ? ? ? ? = ? 2 2 sec sec a k lsb on accelerati input lsbs in errors [ ] lsbs rev lsb rev 2 . 13 sec 000 , 62 2 sec 50 2 14 2 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? reliability the reliability of these products is very high due to the extensive use of custom chip circuits that decrease the active component count. calculations of the m tbf figure under various environ - mental conditions are available up on request from analog devices . figure 9 shows the mtbf in years vs. case temperature for naval s heltered conditions calculated in accordance with the mil - hdbk - 217 e . temper a ture ( c) mtbf ( ears) 100 10 1 25 65 45 85 105 125 02947-009 figure 9 . mtbf vs. temperature processing for high reliability (b suffi x) as a part of the high reliability manufacturing procedure, all converters receive the processing shown in tabl e 6 . table 6. proces s 1 conditions precap v isual i nspection mil - std -883, m ethod 2017 temperature c ycling 10 c ycles, C 65c to +150c constant a cceleration 5000 g s, y1 plane interim e lectrical t ests @ 25c operating b urn i n 160 hours @ 125c se al t est, f ine and g ross mil - std -883, m ethod 1014 final e lectrical t est performed at t min , t amb , t max external v isual i nspection mil - std -883, m ethod 2009 1 test and screening data supplied by request . other products analog devices manufacture s many oth er products concerned with the conversion of synchro/resolver data , such as t he sdc/rdc1740 series and t he ad2s80a series. hybrid the sdc/rdc1740 is a hybrid synchro/resolver - to - digital c onverter with internal isolating micro transformers. m onolithic the ad2s80a series are ics performing resolver - to - digital conversion with accuracies up to 2 arc minutes and 16 - bit resolution.
data sheet ad2s44 rev. b | page 11 of 12 outline dimensions notes: 1. index area is indicated by a notch or lead one identification mark located adjacent to lead one. 2. controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 0.023 (0.58) 0.014 (0.36) 0.910 (23.11) 0.890 (22.61) 1 16 17 32 1.728 (43.89) max 0.225 (5.72) max 0.025 (0.64) 0.015 (0.38) 0.015 (0.38) 0.008 (0.20) 1.102 (27.99) 1.079 (27.41) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 0.120 (3.05) max pin 1 indicator (note 1) 0.192 (4.88) 0.152 (3.86) 0.206 (5.23) 0.186 (4.72) 0.025 (0.64) min figure 10 . 32 - lead bottom - brazed ceramic dip for hybrid [bbdip_h] (dh - 32e) dim ensions shown in inches and ( millimeters ) ordering guide model temperature range package description package option ad2s44 C tm11b ?55 c to +125c 32- lead bottom - brazed ceramic dip for hybrid [bbdip_h] dh-32e ad2s44 C tm12b ?55 c to +125c 32- lead bottom - brazed ceramic dip for hybrid [bbdip_h] dh-32e ad2s44 C tm18b ?55 c to +125c 32- lead bottom - brazed ceramic dip for hybrid [bbdip_h] d h -32e ad2s44 C um18b ?55 c to +125c 32- lead bottom - brazed ceramic dip for hybrid [bbdip_h] dh-32e ordering information when ordering, the converter part numbers are to be suffixed by a two - letter code defining the accuracy grade, and a two digit numeri c code defining the signal/reference voltage and frequency. all the standard options, and their option codes, are shown in figure 11 . for nonstandard configurations, contact analog devices. for example, the ad2s44 C tm12b is the co rrec t part number for a component that oper ate s with 90 v signal, 115 v reference synchro format inputs and yield s a 4.0 a rc m inute s accuracy over the ? 55c to +125c temperature range processed to high reliability standards . ad2s44- base p art number high-re l processing xm y b z 02947-002 *mode l is obsolete and no longer av ailable. z = 0* signal, 2v reference, 2v resolver z = 1 signal, 11.8v reference, 26v synchro z = 2 signal, 90v reference, 115v synchro z = 3* signal, 11.8v reference, 11.8v resolver z = 4* signal, 26v reference, 26v resolver base part z = 8 signal, 11.8v reference, 26v resolver y = 1 400hz to 2.6khz reference frequency x = u ?55c to +125c operating temperature range 4.0 arc min accuracy 2.6 arc min accuracy (?25c to +85c) x = t ?55c to +125c operating temperature range 4.0 arc min accuracy x = s* ?55c to +125c operating temperature range 5.2 arc min accuracy figure 11 .
ad2s44 data sheet rev. b | page 12 of 12 ? 1989 C 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d02947 - 0- 10/11(b) notes

▲Up To Search▲

Price & Availability of AD2S44-TM11B

	To Download AD2S44-TM11B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .